The present application claims priority from Korean patent application no. 2001-68219, filed Nov. 2, 2001, which is incorporated by reference.
1. Technical Field
The present invention relates to a structure and a fabrication method of a storage capacitor used in pixel region of a liquid crystal display (LCD) panel or an organic electronic luminescent display (OELD) panel. More particularly, the invention relates to a technique of simultaneously forming a crystalline silicon pixel transistor and a storage capacitor using metal induced lateral crystallization (MILC) in pixel region of a thin film transistor (TFT) panel for an LCD or an OELD.
2. Background of the Invention
FIG. 1 schematically illustrates a TFT panel 10 for an LCD including a pixel region 11 and a driving circuit region 12 located in the periphery of the pixel region. When the amorphous silicon layer of a TFT formed on a substrate is crystallized by MILC, the electron mobility of the silicon layer is significantly increased. Using the crystallized silicon layer, a plurality of pixel arrays including a pixel transistor and a storage capacitor may be formed in the pixel region 11. At the same time, driving circuit elements may be formed in the driving circuit region 12. For polycrystalline silicon TFT LCD, hybrid driving methods are widely used. In a hybrid type LCD panel, certain analog circuits such as OP amplifier and DA converter, which are difficult to fabricate with polycrystalline silicon, are provide by using separate integrated circuits, and switching elements such as multiplexer are directly formed on the substrate.
FIG. 2 is an equivalent circuit diagram of a pixel unit formed in the pixel region of the LCD TFT panel 10 illustrated in FIG. 1. Each unit pixel includes a data bus line (Vd); a gate bus line (Vg); a pixel TFT comprising a gate connected to the gate bus line, a source and a drain respectively connected to the data bus line and a pixel electrode; a storage capacitor (Cst) 22 for maintaining the state of the signal applied to a pixel TFT 22; and a liquid crystal (CLC) connected in parallel with the storage capacitor. The storage capacitor and the liquid crystal are connected to a common electrode (VCOM) 24. When a unit pixel is selected by the gate bus signal and voltage is applied by the data bus signal, a storage capacitor 22 connected to a drain of a pixel transistor 21 stores electric charge and maintains the voltage applied to the liquid crystal until next signal is applied. Without a storage capacitor, a driving voltage applied by a pixel transistor may not be maintained until the next signal period. Then, continuous display may not be performed.
OELD panel has a condenser structure including a surface glass comprising a transparent glass and transparent electrode; a metal electrode used as a cathode; and an organic luminescent layer interposed between the transparent electrode and the metal electrode. When voltage is applied between the electrodes, the organic luminescent layer emits light through the surface glass. LCD panels including TFT LCD panel have several limitations such as low response speed, narrow vision angle and high power consumption due to a backlight unit. Because OELD panel is a self-light-emitting device, it has advantages of high response speed, high luminescence, low profile structure and low power consumption.
FIG. 3 is a schematic diagram of an OELD TFT panel 30 including pixel region 31 and a driving circuit region 32 formed in the periphery of the pixel region. When the silicon active layer of the TFT is crystallized by MILC, the electron mobility of the active layer is increased. Thus, using MILC crystallization technique, driving circuit elements of high operation speed can be simultaneously formed in the driving circuit region when forming a plurality of pixel arrays including addressing transistor, storage capacitor and pixel driving transistor in the pixel region 31. As the case of LCD panel, hybrid driving methods are frequently used for driving OELD TFT panels.
FIG. 4A is an equivalent circuit diagram of a unit pixel formed in the pixel region of a voltage-driven type OELD TFT panel 30. Each unit pixel includes a data bus line (Vd); a gate bus line (Vg); and an addressing (switching) TFT comprising a gate connected to the gate bus line and a source and a drain connected to the data bus line. The drain of the addressing TFT 41 is connected to the gate of a pixel driving TFT 43 for receiving a reference voltage (Vdd) and providing a driving voltage (Vc) to organic luminescent material layer. A storage capacitor 42 for maintaining the signal applied to the gate of the pixel driving TFT is also connected in parallel with the pixel driving TFT 43. Since TFT LCD is not a self-light-emitting type device, only one pixel TFT is used in a unit pixel to provide a voltage to a pixel electrode. However, in OELD, data signal may not provide a voltage required to induce the light emission of the organic material. Thus, it has to use a separate pixel driving TFT 43 receiving the output signal of the addressing TFT 41 as a gate signal.
FIG. 4B illustrates an example of the equivalent circuit diagram of a unit pixel in the pixel region of a current-driven type OELD TFT panel 30. A unit pixel of a current-driven type OELD TFT panel includes two addressing TFT""s 44, 45, two pixel driving TFT""s 47, 48 and one storage capacitor 46. A first addressing TFT 44 is turned on by a signal of a first gate bus line (Vg1) to receive a signal of the data bus line (Vd). A second addressing TFT 45 is turned on by a signal of a first gate bus line (Vg2) and provides the output of the first addressing TFT 44 to the gates of a pair of pixel driving TFT""s 47, 48 and to the storage capacitor 46. When electric charge is accumulated in the storage capacitor 46 after the first addressing TFT 44 and the second addressing TFT 45 are turned on, the voltage created in the storage capacitor is applied to the gates of the first and the second pixel driving TFT""s 47, 48 to turn on the pixel driving TFT""s. The voltage applied by the storage capacitor is maintained even when the second addressing TFT is turned off. Thus the turn on state of the pixel driving TFT""s 47, 48 is maintained until the next signal period and they continue to provide the driving current to the unit pixel.
As can be seen from FIGS. 2, 4A and 4B, a storage capacitor for LCD TFT panel or OELD TFT panel is connected to an LCD pixel TFT or to the drain of an OELD addressing TFT (a second addressing TFT for an current-driven type). FIGS. 5A and 5B are a plan view and a sectional view of an LCD pixel TFT or an OELD addressing TFT including a polycrystalline silicon active layer crystallized by MILC, which is connected to a storage capacitor simultaneously formed with the TFT. FIGS. 5A and 5B show a thin film transistor in the left-hand side and a capacitor structure in the right-hand side. The TFT is used as a pixel TFT in an LCD panel and as an addressing TFT in a unit pixel of an OELD panel. The TFT may be used as a second addressing TFT 45 in current-driven type OELD panel as shown in FIG. 4B. In FIGS. 5A and 5B, a drain of the TFT is directly connected to a silicon layer of the capacitor. In actual pixel layout of LCD or OELD, however, they may not be physically connected with each other. Instead, they may be electrically connected with each other by wire.
On the transparent substrate 51, a buffer layer 52 for preventing diffusion of impurities from the substrate 51 is formed. On the buffer layer, an amorphous silicon layer 53 is patterned and a gate insulating layer 54 and a capacitor dielectric layer 55 are formed on the patterned silicon layer. Thereafter, a gate electrode layer 56 and a capacitor electrode 57 are formed on the gate insulating layer and the dielectric layer, respectively. As such, a TFT structure including an amorphous silicon layer 53, gate insulating layer 54 and a gate electrode 56, which may be used as a pixel TFT for an LCD panel or an addressing TFT for an OELD panel, is formed on the left side. On the right side of the TFT, a storage capacitor including a amorphous silicon layer 53 connected to the drain of the TFT, a dielectric layer 55 and a capacitor electrode 57 is formed. After forming a TFT and a storage capacitor as described above, N type or P type dopant is injected into the silicon layer by using low-energy high-concentration doping process and high-energy low-concentration doping process using the gate insulating layer 54, the gate electrode 56, the dielectric layer 55 and the capacitor electrode as a mask. Then a lightly doped region 58 such as LDD (lightly doped drain) region is formed in the silicon layer of the TFT in the region covered with the gate insulating layer around the channel region. An LDD region formed in a TFT has effects of reducing the off current and improving other electrical characteristics of the TFT. A lightly doped region 59 may also be formed in a part of the capacitor region under the dielectric layer 55. The lightly doped region 59, however, does not affect the performance of the capacitor. High concentration of impurity is doped in the amorphous silicon region 60, 60xe2x80x2 on both sides of the gate insulating layer 54 to form source 60 and drain 60xe2x80x2 region of a TFT.
A process of crystallizing the amorphous silicon layer as shown in FIGS. 5A and 5B by means of MILC will be described below. Polycrystalline silicon TFT panels for LCD or OELD were conventionally fabricated by crystallizing an amorphous silicon layer using solid phase crystallization (SPC), laser crystallization, rapid thermal annealing (RTA), and the like. These methods, however, tend to cause damages to the substrate and fail to provide satisfactory uniformity of crystal quality. These limitations pose difficulties in the fabrication of polycrystalline silicon TFT panel. To overcome the aforementioned disadvantages of the conventional silicon crystallization methods, a method of inducing crystallization of an amorphous silicon layer at a low temperature about 200xc2x0 C. by contacting or implanting metals such as nickel, gold, and aluminum has been proposed. This phenomenon that low-temperature crystallization of amorphous silicon is induced with metal is conventionally called as metal induced crystallization (MIC). However, this metal induced crystallization (MIC) method also has following disadvantages. If a TFT is manufactured by the MIC method, the metal component used to induce the crystallization of silicon remains in the crystallized silicon providing the active layer of the TFT. The metal component remaining in the active layer causes current leakage in the channel region of the TFT.
Recently, a method of crystallizing a silicon layer by inducing crystallization of amorphous silicon in the lateral direction using a metal, which is conventionally refereed to as xe2x80x9cmetal induced lateral crystallizationxe2x80x9d (MILC), was proposed. (See S. W. Lee and S. K. Joo, IEEE Electron Device Letter, 17(4), p. 160, 1996) In the metal induced lateral crystallization (MILC) phenomenon, metal does not directly cause the crystallization of the silicon, but the silicide generated by a chemical reaction between metal and silicon induces the crystallization of the silicon. As the crystallization proceeds, the silicide propagates in the lateral direction of the silicon inducing the sequential crystallization of the adjacent silicon region. As the metal causing this MILC, nickel and palladium or the like are known to those skilled in the art. Crystallizing a silicon layer by the MILC, a silicide containing crystallization inducing metal moves along the lateral direction as the crystallization of the silicon layer proceeds. Accordingly, little metal component is left in the silicon layer crystallized by the MILC. Therefore, the crystallized silicon layer does not adversely affect the current leakage or other characteristics of the TFT including the silicon layer. In addition, using the MILC, crystallization of silicon may be induced at a relatively low temperature of 300xc2x0 C.xcx9c500xc2x0 C. Thus, a plurality of substrates can be crystallized in a furnace at one time without causing any damages to the substrates.
FIG. 6 illustrates a state where a metal layer 61 composed of metal such as Ni, Pd for inducing MILC of amorphous silicon is formed over the entire surface of the substrate using sputtering. The MILC inducing metal causes crystallization of silicon layer by MIC in the region directly contacting the metal. Other regions of the silicon layer not covered with the MILC inducing metal such as the regions under the gate insulating layer 54 and the dielectric layer 55 are crystallized by MILC propagating from the regions crystallized by MIC. The MILC inducing metal deposited on the gate insulating layer 54, gate electrode 56, the dielectric layer 57 and the capacitor electrode 57 does not affect the crystallization of the amorphous silicon layer since it does not react with insulating material or metal.
A substrate covered with MILC inducing metal is subjected to heat treatment at a temperature in the range of 300xc2x0 C. to 600xc2x0 C. Portions of amorphous silicon layer directly covered with the MILC inducing metal are crystallized by MIC and the remaining portion of amorphous silicon layer not covered with the MILC inducing metal is crystallized by MILC propagating from the portions covered with the MILC inducing metal. The arrows in FIG. 6 indicate the propagation direction of MILC. Typically, the channel width xe2x80x9caxe2x80x9d corresponding to the width of the gate electrode is about 10 xcexcm and the width of the dielectric layer of the storage capacitor is about 15-30 xcexcm. As shown in FIG. 6, the channel region of the TFT is crystallized by MILC propagating from both sides of the channel region and the amorphous silicon layer in the capacitor area is crystallized by the MILC propagating in one direction, that is, from the drain of the TFT. Therefore, the TFT channel region can be crystallized within a time during which MILC propagates by 5 xcexcm in amorphous silicon. Meanwhile, it requires a time during which MILC propagates 15-30 xcexcm in amorphous silicon to crystallize the amorphous silicon layer in the capacitor region. The silicon layer in the capacitor region crystallized by MILC constitutes a conducting layer facing the capacitor electrode 57 from both sides of the dielectric layer 55. If the crystallization by MILC is terminated before the entire area of the amorphous silicon in the capacitor region is crystallized, the area of the conducting layer becomes smaller than the designed area. Then the storage capacitor may not have desired capacitance. If the amorphous silicon layer in the capacitor region is crystallized by MILC propagating in one direction, the MILC process has to be continued until the crystallization front of MILC completely traverse the entire width of capacitor region. The long duration of crystallization process reduces the productivity of the TFT fabrication and increases the possibility that thermal damages are caused to the substrate.
Therefore, it is an object of the present invention to solve these problems as mentioned above, more particularly, to provide a storage capacitor structure and a fabrication method thereof that may simultaneously form a storage capacitor with an LCD pixel TFT or with an OELD addressing TFT and may reduce the time required to crystallize the silicon layer of the storage capacitor.
According to one aspect of the present invention, there is provided a crystalline silicon TFT panel for a TFT LCD panel, comprising a transparent substrate including a plurality of unit pixel region; a pixel transistor formed in each of the unit pixel region and including a crystalline silicon active layer, a gate insulating layer and a gate electrode which are sequentially formed on the substrate; and a storage capacitor formed in each of the unit pixel region and including a crystalline silicon layer, a dielectric layer and a capacitor electrode which are sequentially formed on the substrate. The crystalline silicon layers of the pixel transistor and the storage capacitor are simultaneously formed by depositing an amorphous silicon layer, applying MILC inducing metal on at least a portion of the amorphous silicon layer and conducting a thermal treatment; and the crystalline silicon layer of said storage capacitor extends outwardly from the outer boundary of the dielectric layer in at least two directions; and the MILC inducing metal is applied on the portions of the silicon layer extending from the outer boundary of the dielectric layer.
The present invention may fabricate a storage capacitor during the process of forming a pixel transistor in the unit pixel region without introducing any additional process. By applying the MILC inducing metal along the boundary of the dielectric layer, the present invention may reduce the time required to crystallize the silicon layer of the storage capacitor. The inventive technique can be also applied to fabrication of a crystalline TFT panel for an OELD panel.